`timescale 1ns/1ns   //1ns ->  0.01ms
module zl_2346_6_test;
 
	// Inputs
	reg clk;
	reg rst_n;
	reg key_in;
 
	// Outputs
	wire key_flag;
	wire key_state;
	wire [11:0]cnt_out;
 
	// Instantiate the Unit Under Test (UUT)
	zl_2346_6 uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.key_in(key_in), 
		.key_flag(key_flag), 
		.key_state(key_state),
		.cnt_out(cnt_out)
	);
always #5 clk = ~clk;
	initial begin
		clk = 1'b0;
		rst_n = 1'b0;
		key_in = 1'b1;
		#20;
        rst_n = 1'b1;
	end
   always begin
		#100;
		key_in=1'b1;
		#100;
		key_in=1'b0;
		#100;
		key_in=1'b1;
		#100;
		key_in=1'b0;
		#100;
		key_in=1'b1;
		#100;
		key_in=1'b0;
		#100;
		key_in=1'b1;
		#100;
		key_in=1'b0;
		#100;
		key_in=1'b1;
		#100;
		key_in=1'b0;
		#(50*100);
		key_in=1'b1;
		
		#100;
		key_in=1'b0;
		#100;
		key_in=1'b1;
		#100;
		key_in=1'b0;
		#100;
		key_in=1'b1;
		#100;
		key_in=1'b0;
		#100;
		key_in=1'b1;
		#100;
		key_in=1'b0;
		#100;
		key_in=1'b1;
		#100;
		key_in=1'b0;
		#100;
		key_in=1'b1;
		#(50*100);
		key_in=1'b0;
	end
endmodule